Semiconductor & Microelectronics IP

Semiconductor Patents Need Real Engineers

Semiconductor patent claims are among the most technically complex intellectual property in existence. A claim covering "a field-effect transistor comprising a gate dielectric layer having a dielectric constant greater than 3.9 and a channel region comprising a plurality of horizontally-stacked silicon nanosheets" demands immediate understanding of high-k dielectric physics, GAAFET nanosheet architecture, and ALD manufacturing processes — before a single search query can be meaningfully formulated.

Without engineering depth, "searching" this claim means typing keywords and hoping the relevant prior art uses identical terminology. It will not. The 1990s research papers describing horizontal nanosheet channel formation using different materials for different purposes are the critical prior art — and finding them requires knowing they are relevant to this claim.

The Transistor Scaling Crisis — FinFET to GAAFET

For five decades, transistor scaling followed Moore's Law. By the 22nm node, however, planar transistors suffered catastrophic short-channel effects: threshold voltage roll-off, drain-induced barrier lowering (DIBL), and collapsing gate-to-channel electrostatic control. Intel's 22nm FinFET (2011) formed the channel as a vertical silicon fin surrounded by the gate on three sides — dramatically improving electrostatic control. TSMC and Samsung adopted FinFET at 16nm/14nm. But below 5nm, fin width must be narrowed to the point where quantum mechanical effects and manufacturing variability make FinFET unviable.

The solution is the Gate-All-Around FET (GAAFET) — specifically the nanosheet transistor. Horizontal silicon nanosheets (5-8nm thick) are stacked vertically. The gate material completely wraps all four sides of each nanosheet, achieving maximum electrostatic control. Samsung introduced nanosheet MBCFET™ at 3nm (2022). TSMC implemented N2 GAA in 2025. Intel's RibbonFET follows the same principle.

Nanosheet Patent Battlegrounds

The FinFET-to-GAAFET transition has triggered the most intensive semiconductor patent wave since the integrated circuit itself:

• SiGe/Si superlattice formation — Alternating silicon and silicon-germanium epitaxial layers. SiGe is the sacrificial layer; pure Si becomes the nanosheet channel. Composition ratio, strain, and selective etch chemistry are all heavily patented.
• Inner spacer formation — Isolating gate material from source/drain contacts between nanosheet layers. Inner spacer recess depth and material determine leakage current and parasitic capacitance — a critical differentiator between foundry implementations.
• Conformal high-k dielectric ALD — Hafnium oxide (HfO₂) conformally deposited inside nanosheet stacks at sub-angstrom thickness precision. The uniformity challenge inside stacked sheets is extraordinary.
• Bottom dielectric isolation (BDI) — Preventing leakage between the bottom nanosheet and substrate — a genuine manufacturing innovation with no clear prior art equivalent.
• Complementary FET (CFET) — Stacking p-type and n-type GAAFET vertically in a single device height — the next major density-scaling leap and currently the subject of racing patent filings from all major foundries.

Advanced Packaging — Chiplets and 3D-IC

As front-end scaling costs escalate, the industry has pivoted to advanced packaging as the primary scaling mechanism. Chiplet architecture disaggregates large SoCs into smaller separately-fabricated dies interconnected in a single package — enabling heterogeneous integration: logic at 3nm, memory at mature nodes, RF at GaAs, all combined. TSMC's CoWoS uses a silicon interposer with TSVs for die-to-die interconnect. SoIC uses hybrid bonding — direct copper-to-copper at sub-2μm pitch. HBM4 (high bandwidth memory) stacks DRAM dies on an AI accelerator through a 2.5D interposer. Each interconnect innovation generates its own patent wave covering TSV structure, interface protocol, power delivery, and thermal management.

GaN and SiC — The Wide Bandgap Power Revolution

Silicon's 1.1 eV bandgap limits power device voltage and frequency. SiC (3.3 eV bandgap, 2,200V/μm breakdown) and GaN (3.4 eV, 3,300V/μm) overcome these limits fundamentally. Tesla's Model 3 was the first mass-market EV with SiC MOSFETs in its traction inverter — achieving 5-8% better system efficiency. GaN enables 100W+ USB-PD chargers in brick-sized form factors by switching 10-100x faster than silicon. Both materials have dense overlapping patent portfolios covering substrate growth, epitaxy, device structure, gate driver circuits, and packaging.